OVMSA-2020-0026 - microcode_ctl security update
| Type: | SECURITY |
| Severity: | IMPORTANT |
| Release Date: | 2020-06-19 |
Description
[3:1.17-33.26.0.1]
- update 06-2d-07 to 0x71a
- update 06-55-04 to 0x2006906
- update 06-55-07 to 0x5002f01
- merge Oracle changes for early load via dracut
- enable late load on install for UEK4 kernels marked safe (except BDW-79)
- set early_microcode='no' in virtualized guests to avoid early load bugs [Orabug: 30618737]
[2:1.17-33.26]
- Update Intel CPU microcode to microcode-20200602 release, addresses
CVE-2020-0543, CVE-2020-0548, CVE-2020-0549 (#1795353, #1795357, #1827186):
- Update of 06-3c-03/0x32 (HSW C0) microcode from revision 0x27 up to 0x28;
- Update of 06-3d-04/0xc0 (BDW-U/Y E0/F0) microcode from revision 0x2e
up to 0x2f;
- Update of 06-45-01/0x72 (HSW-U C0/D0) microcode from revision 0x25
up to 0x26;
- Update of 06-46-01/0x32 (HSW-H C0) microcode from revision 0x1b up to 0x1c;
- Update of 06-47-01/0x22 (BDW-H/Xeon E3 E0/G0) microcode from revision 0x21
up to 0x22;
- Update of 06-4e-03/0xc0 (SKL-U/Y D0) microcode from revision 0xd6
up to 0xdc;
- Update of 06-55-03/0x97 (SKX-SP B1) microcode from revision 0x1000151
up to 0x1000157;
- Update of 06-55-04/0xb7 (SKX-SP H0/M0/U0, SKX-D M1) microcode
(in intel-06-55-04/intel-ucode/06-55-04) from revision 0x2000065
up to 0x2006906;
- Update of 06-55-06/0xbf (CLX-SP B0) microcode from revision 0x400002c
up to 0x4002f01;
- Update of 06-55-07/0xbf (CLX-SP B1) microcode from revision 0x500002c
up to 0x5002f01;
- Update of 06-5e-03/0x36 (SKL-H/S R0/N0) microcode from revision 0xd6
up to 0xdc;
- Update of 06-8e-09/0x10 (AML-Y22 H0) microcode from revision 0xca
up to 0xd6;
- Update of 06-8e-09/0xc0 (KBL-U/Y H0) microcode from revision 0xca
up to 0xd6;
- Update of 06-8e-0a/0xc0 (CFL-U43e D0) microcode from revision 0xca
up to 0xd6;
- Update of 06-8e-0b/0xd0 (WHL-U W0) microcode from revision 0xca
up to 0xd6;
- Update of 06-8e-0c/0x94 (AML-Y42 V0, CML-Y42 V0, WHL-U V0) microcode
from revision 0xca up to 0xd6;
- Update of 06-9e-09/0x2a (KBL-G/H/S/X/Xeon E3 B0) microcode from revision
0xca up to 0xd6;
- Update of 06-9e-0a/0x22 (CFL-H/S/Xeon E3 U0) microcode from revision 0xca
up to 0xd6;
- Update of 06-9e-0b/0x02 (CFL-S B0) microcode from revision 0xca up to 0xd6;
- Update of 06-9e-0c/0x22 (CFL-H/S P0) microcode from revision 0xca
up to 0xd6;
- Update of 06-9e-0d/0x22 (CFL-H R0) microcode from revision 0xca up to 0xd6.
[2:1.17-33.25]
- Update Intel CPU microcode to microcode-20200520 release (#1839193):
- Update of 06-2d-06/0x6d (SNB-E/EN/EP C1/M0) microcode from revision 0x61f
up to 0x621;
- Update of 06-2d-07/0x6d (SNB-E/EN/EP C2/M1) microcode from revision 0x718
up to 0x71a;
- Update of 06-7e-05/0x80 (ICL-U/Y D1) microcode from revision 0x46
up to 0x78.
[2:1.17-33.24]
- Narrow down SKL-SP/W/X blacklist to exclude Server/FPGA/Fabric segment
models (#1835555).
[2:1.17-33.23]
- Do not update 06-55-04 (SKL-SP/W/X) to revision 0x2000065, use 0x2000064
by default (#1774635).
[2:1.17-33.22]
- Update Intel CPU microcode to microcode-20191115 release:
- Update of 06-4e-03/0xc0 (SKL-U/Y D0) from revision 0xd4 up to 0xd6;
- Update of 06-5e-03/0x36 (SKL-H/S/Xeon E3 R0/N0) from revision 0xd4
up to 0xd6;
- Update of 06-8e-09/0x10 (AML-Y 2+2 H0) from revision 0xc6 up to 0xca;
- Update of 06-8e-09/0xc0 (KBL-U/Y H0) from revision 0xc6 up to 0xca;
- Update of 06-8e-0a/0xc0 (CFL-U 4+3e D0) from revision 0xc6 up to 0xca;
- Update of 06-8e-0b/0xd0 (WHL-U W0) from revision 0xc6 up to 0xca;
- Update of 06-8e-0c/0x94 (AML-Y V0, CML-U 4+2 V0, WHL-U V0) from revision
0xc6 up to 0xca;
- Update of 06-9e-09/0x2a (KBL-G/X H0, KBL-H/S/Xeon E3 B0) from revision 0xc6
up to 0xca;
- Update of 06-9e-0a/0x22 (CFL-H/S/Xeon E U0) from revision 0xc6 up to 0xca;
- Update of 06-9e-0b/0x02 (CFL-S B0) from revision 0xc6 up to 0xca;
- Update of 06-9e-0c/0x22 (CFL-S/Xeon E P0) from revision 0xc6 up to 0xca;
- Update of 06-9e-0d/0x22 (CFL-H/S R0) from revision 0xc6 up to 0xca;
- Update of 06-a6-00/0x80 (CML-U 6+2 A0) from revision 0xc6 up to 0xca.
[2:1.17-33.21]
- Update Intel CPU microcode to microcode-20191113 release:
- Update of 06-9e-0c (CFL-H/S P0) microcode from revision 0xae up to 0xc6.
- Drop 0001-releasenote-changes-summary-fixes.patch.
[2:1.17-33.20]
- Package the publicy available microcode-20191112 release (#1755021):
- Addition of 06-4d-08/0x1 (AVN B0/C0) microcode at revision 0x12d;
- Addition of 06-55-06/0xbf (CSL-SP B0) microcode at revision 0x400002c;
- Addition of 06-7a-08/0x1 (GLK R0) microcode at revision 0x16;
- Update of 06-55-03/0x97 (SKL-SP B1) microcode from revision 0x1000150
up to 0x1000151;
- Update of 06-55-04/0xb7 (SKL-SP H0/M0/U0, SKL-D M1) microcode from revision
0x2000064 up to 0x2000065;
- Update of 06-55-07/0xbf (CSL-SP B1) microcode from revision 0x500002b
up to 0x500002c;
- Update of 06-7a-01/0x1 (GLK B0) microcode from revision 0x2e up to 0x32;
- Include 06-9e-0c (CFL-H/S P0) microcode from the microcode-20190918 release.
- Correct the releasenote file (0001-releasenote-changes-summary-fixes.patch).
- Update README.caveats with the link to the new Knowledge Base article.
[2:1.17-33.19]
- Fix the incorrect 'Source2:' tag.
[2:1.17-33.18]
- Intel CPU microcode update to 20191112, addresses CVE-2017-5715,
CVE-2019-0117, CVE-2019-11135, CVE-2019-11139 (#1764049, #1764062, #1764953,
- Addition of 06-a6-00/0x80 (CML-U 6+2 A0) microcode at revision 0xc6;
- Addition of 06-66-03/0x80 (CNL-U D0) microcode at revision 0x2a;
- Addition of 06-55-03/0x97 (SKL-SP B1) microcode at revision 0x1000150;
- Addition of 06-7e-05/0x80 (ICL-U/Y D1) microcode at revision 0x46;
- Update of 06-4e-03/0xc0 (SKL-U/Y D0) microcode from revision 0xcc to 0xd4;
- Update of 06-5e-03/0x36 (SKL-H/S/Xeon E3 R0/N0) microcode from revision 0xcc
to 0xd4
- Update of 06-8e-09/0x10 (AML-Y 2+2 H0) microcode from revision 0xb4 to 0xc6;
- Update of 06-8e-09/0xc0 (KBL-U/Y H0) microcode from revision 0xb4 to 0xc6;
- Update of 06-8e-0a/0xc0 (CFL-U 4+3e D0) microcode from revision 0xb4
to 0xc6;
- Update of 06-8e-0b/0xd0 (WHL-U W0) microcode from revision 0xb8 to 0xc6;
- Update of 06-8e-0c/0x94 (AML-Y V0) microcode from revision 0xb8 to 0xc6;
- Update of 06-8e-0c/0x94 (CML-U 4+2 V0) microcode from revision 0xb8 to 0xc6;
- Update of 06-8e-0c/0x94 (WHL-U V0) microcode from revision 0xb8 to 0xc6;
- Update of 06-9e-09/0x2a (KBL-G/X H0) microcode from revision 0xb4 to 0xc6;
- Update of 06-9e-09/0x2a (KBL-H/S/Xeon E3 B0) microcode from revision 0xb4
to 0xc6;
- Update of 06-9e-0a/0x22 (CFL-H/S/Xeon E U0) microcode from revision 0xb4
to 0xc6;
- Update of 06-9e-0b/0x02 (CFL-S B0) microcode from revision 0xb4 to 0xc6;
- Update of 06-9e-0d/0x22 (CFL-H R0) microcode from revision 0xb8 to 0xc6.
[2:1.17-33.17]
- Do not update 06-2d-07 (SNB-E/EN/EP) to revision 0x718, use 0x714
by default (#1758382).
[2:1.17-33.16]
- Revert more strict model check code, as it requires request_firmware-based
microcode loading mechanism and breaks enabling of microcode with caveats.
[2:1.17-33.15]
- Intel CPU microcode update to 20190918 (#1753540).
[2:1.17-33.14]
- Intel CPU microcode update to 20190618 (#1717238).
[2:1.17-33.13]
- Remove disclaimer, as it is not as important now to justify kmsg/log
pollution; its contents are partially adopted in README.caveats.
[2:1.17-33.12]
- Intel CPU microcode update to 20190514a (#1711938).
[2:1.17-33.11]
- Intel CPU microcode update to 20190507_Public_DEMO (#1697960).
[2:1.17-33.10]
- Intel CPU microcode update to 20190312 (#1697960).
[2:1.17-33.9]
- Fix disclaimer path in %post script.
[2:1.17-33.8]
- Fix installation path for the disclaimer file.
- Add README.caveats documentation file.
[2:1.17-33.7]
- Use check_caveats from the RHEL 7 package in order to support overrides.
[2:1.17-33.6]
- Disable 06-4f-01 microcode in config (#1622180).
[2:1.17-33.5]
- Intel CPU microcode update to 20180807a (#1614427).
- Add check for minimal microcode version to reload_microcode.
[2:1.17-33.4]
- Intel CPU microcode update to 20180807.
- Resolves: #1614427.
[2:1.17-33.3]
- Intel CPU microcode update to 20180703
- Add infrastructure for handling kernel-version-dependant microcode
- Resolves: #1574593
[1:1.17-33.1]
- Intel CPU microcode update to 20180613.
- Resolves: #1573451
[1:1.17-33]
- Update AMD microcode to 2018-05-24
- Resolves: #1584192
[1:1.17-32]
- Update AMD microcode
- Resolves: #1574591
[1:1.17-31]
- Update disclaimer text
- Resolves: #1574588
[1:1.17-30]
- Intel CPU microcode update to 20180425.
- Resolves: #1574588
[1:1.17-29]
- Revert Microcode from Intel and AMD for Side Channel attack
- Resolves: #1533941
[1:1.17-28]
- Update microcode data file to 20180108 revision.
- Resolves: #1527354
[1:1.17-27]
- Update Intel CPU microde for 06-3f-02, 06-4f-01, and 06-55-04
- Add amd microcode_amd_fam17h.bin data file
- Resolves: #1527354
[1:1.17-26]
- Update microcode data file to 20170707 revision.
- Resolves: #1465143
[1:1.17-25]
- Revert microcode_amd_fam15h.bin to version from amd-ucode-2012-09-10
- Resolves: #1322525
[1:1.17-24]
- Update microcode data file to 20161104 revision.
- Add workaround for E5-26xxv4
- Resolves: #1346045
[1:1.17-23]
- Update microcode data file to 20160714 revision.
- Resolves: #1346045
[1:1.17-22]
- Update amd microcode data file to amd-ucode-2013-11-07
- Resolves: #1322525
[1:1.17-21]
- Update microcode data file to 20151106 revision.
- Resolves: #1244968
- Remove bad file permissions on /lib/udev/rules.d/89-microcode.rules
- Resolves: #1201276
[1:1.17-20]
- Update microcode data file to 20150121 revision.
- Resolves: #1123992
[1:1.17-19]
- Update microcode data file to 20140624 revision.
- Resolves: #1113394
[1:1.17-18]
- Update microcode data file to 20140430 revision.
- Resolves: #1036240
Related CVEs
Updated Packages
| Release/Architecture | Filename | MD5sum | Superseded By Advisory |
|
| Oracle VM 3.3 (x86_64) | microcode_ctl-1.17-33.26.0.1.el6_10.src.rpm | 930b95fe9223e3e892dc93386eced322 | OVMSA-2020-0053 |
| microcode_ctl-1.17-33.26.0.1.el6_10.x86_64.rpm | 55d98a32f6b68d554c8b1833d730879c | OVMSA-2020-0053 |
|
| Oracle VM 3.4 (x86_64) | microcode_ctl-1.17-33.26.0.1.el6_10.src.rpm | 930b95fe9223e3e892dc93386eced322 | OVMSA-2020-0053 |
| microcode_ctl-1.17-33.26.0.1.el6_10.x86_64.rpm | 55d98a32f6b68d554c8b1833d730879c | OVMSA-2020-0053 |
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